Transistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) or MOS transistors are the core building blocks of the vast majority of semiconductor integrated circuits (ICs). A FET includes source and drain regions between which a current can flow through a channel under the influence of a bias applied to a gate electrode that overlies the channel. Some semiconductor ICs, such as high performance microprocessors, can include millions of FETs. For such ICs, decreasing transistor size and thus increasing transistor density has traditionally been a high priority in the semiconductor manufacturing industry. Transistor performance, however, must be maintained even as the transistor size decreases.
A FINFET is a type of transistor that lends itself to the dual goals of reducing transistor size while maintaining transistor performance. The FINFET is a three dimensional transistor formed in a thin fin that extends upwardly from a semiconductor substrate. Transistor performance, often measured by its transconductance, is proportional to the width of the transistor channel. In a FINFET the transistor channel is formed at least along the vertical sidewalls of the fin, so a wide channel, and hence high performance, can be achieved without substantially increasing the area of the substrate surface required by the transistor.
Even with FINFETs, however, reducing device size and hence reducing feature size introduces fabrication problems. Such problems include adverse short channel effects as the gate length shrinks and the attendant variation in threshold voltage (basically the minimum gate voltage necessary to turn a transistor “ON”) from random dopant fluctuations in the channel. Threshold variations, in turn, lead to problems with unmatched transistors. One solution is to fabricate transistors with undoped channels, but fabricating such transistors is difficult, especially with devices formed on a bulk semiconductor wafer and especially when FINFETs are intermixed in an integrated circuit with planar MOSFETs. FINFETs and planar MOSFETs have different characteristics and each possesses certain strengths. To be able to use both in a circuit design allows the circuit designer to take advantage of the strengths of each type of device.
Another problem that is encountered in the fabrication of MOSFET integrated circuits as the device size shrinks is the correct placement of contacts, for example the contacts to the source and drains of individual transistors. As the pitch (the spacing from gate to gate) decreases below a certain dimension, it is important to have a self aligning method for positioning the contacts. In order to reduce series resistance it is also important to form silicided contacts to the source and drain regions. Metal silicides must not be subjected to high temperatures, so the silicided contacts, including self aligned silicided contacts must be formed after most of the high temperature processing steps.
Accordingly, it is desirable to provide methods for fabricating integrated circuits that include both FINFETs and planar MOSFETs. In addition, it is desirable to provide methods for fabricating MOSFET integrated circuits with undoped channel regions. It is also desirable to provide methods for fabricating integrated circuits with self aligned contacts. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.